This disclosure relates generally to current sources and more particularly to current source generator circuits utilizing a portion of a replicated analog circuit.
The power level in certain analog circuits is very important for various applications, especially when a given circuit may be repeated many times on an integrated circuit chip. For example, circuitry associated with an individual pixel (picture element), or row or column of pixels in an image sensor is repeated many times on the chip. Generally, the power level of the circuit will be set by the design to be at the highest level that is needed for specified range of data rates, temperature, power supply voltage and semiconductor process variations. This power design level results in much wasted power for nominal product running at normal environmental operating conditions and/or lower speed operation.
An example of a circuit that is replicated many times is the pixel circuitry shown in FIG. 7. In FIG. 7 there is shown the image sensor array with two stage transfer, designated generally by the numeral 700, of the type to which the present current source generator is directed. Image sensor array 700 includes a base or chip 702 of silicon with a plurality of photosites in the form of photodiodes 704 thereon. Photodiodes 704 are in closely spaced juxtaposition with one another on chip 702 in a linear array or row 706. Several smaller arrays such as array 700 can be abutted together end to end with one another to form a longer array, i.e. a full width or contact array, with spacing between the photodiodes 704 at the butted ends the same as the spacing between the photodiodes 704 inside the chip thereby maintaining photodiode pitch across the entire full width of the composite array.
While photodiodes 704 are shown and described herein, other photosite types such as amorphous silicon or transparent electrode MOS type photosites may be envisioned. Further, while a one dimensional sensor array having a single row 706 of photodiodes 704 is shown and described herein, a two dimensional sensor array with plural rows of photodiodes may be contemplated.
Each photodiode 704 has a two stage transfer circuit 802 associated therewith which together with the photodiode 704 and an amplifier 804 form a photosite cell 800 at the array front end. In each cell 800, the image signal charge from the photodiode 704 is transferred by circuit 802 to amplifier 804 where the image signal charge from photodiode 704 is amplified to bring the image signal charge to a desired potential level prior to transferring the charge to a common video output line or bus 708. Suitable shift register and logic circuitry 710 provide timing control signals ΦPIXEL and ΦSTDBY for connecting each pixel cell 800 to bus 708 in the proper timed sequence.
Image sensor array 700 may for example be used to raster scan a document original, and in that application, the document original and the sensor array 700 are moved or stepped relative to one another in a direction (i.e., the slow scan direction) that is normally perpendicular to the linear axis of array 700. At the same time, the array 700 scans the document original line by line in the direction (i.e., the fast scan direction) parallel to the linear axis of the array. The image line being scanned is illuminated and focused onto the photodiodes 704. During an integration period, a charge is developed on each photodiode 704 proportional to the reflectance of the image area viewed by each photodiode 704. The image signal charges are thereafter transferred by two stage transfer circuits 802 via amplifier 804 to output bus 708 in a predetermined step by step timed sequence. The problem of high current in the pixel amplifier 804 is addressed by low power reset and sequential high power readout of each amplifier 804.
Reference is made to the following U.S. patents, the disclosures of which are hereby incorporated herein by this reference: U.S. Pat. No. 5,493,423, issued Feb. 20, 1996 to Hosier for a Resettable Pixel Amplifier for an Image Sensor Array; U.S. Pat. No. 6,670,598 issued Dec. 30, 2003 to Hosier, et al. for a Low Power Autozero of Pixel Amplifier; U.S. Pat. No. 5,638,121 issued Jun. 10, 1997 to Hosier, et al. for a High-speed Output of Video Image Data From An Array of Photosensors. These patents disclose alternative pixel circuits with which the disclosed current source may be utilized. U.S. Pat. Nos. 5,493,423 and 6,670,598 also explain some considerations for low power in the pixel circuits of the prior image sensors. U.S. Pat. No. 5,638,121 explains another additional method to improve the serial output speed of the image sensor chip with minimum power increase.
Referring particularly to FIG. 8, the two stage transfer circuit 802 associated with each cell 800 includes a reset transistor 806, a cascode amplifier 808, a biasing diode 810, a pass transistor 812 and a hold capacitor CH 44. In the illustrated embodiment, cascode amplifier 808 is configured as a trans-impedance amplifier for transferring the image signal charge from the photodiode 704 to amplifier 804.
A suitable clock source 814, which may include the master clock 12 and portions of the shift register and logic circuitry 710 as well as other components, provides bias voltages VB1, VB2 and VB3 as well as pulses ΦS, ΦRX, ΦPDX, ΦPIXEL and ΦSTDBY. The ΦPIXEL and ΦSTDBY signals for multiplexing the amplified charge output by amplifier 804 onto the common video output bus 708 are typically provided by shift register and logic circuitry 710.
In operation the reset pulse ΦRX actuates reset transistor 806 and ΦPDX actuates pass transistor 812 to read out the integrated voltage from node 824 onto the reset or storage node 830. To read out the video signals from the various amplifiers 804 onto the video bus in an orderly manner, signal pulses ΦPIXEL1, ΦPIXEL2, ΦPIXEL3 . . . activate the respective amplifiers 804 of the replicated circuits 800 in quick succession. After the image signal has been transferred to the reset node input of the amplifier 804, the photodiodes 704 can be reset and biased for the next light integration period. This can occur during the readout of the amplifiers 804.
In the pixel circuitry of FIG. 8, the high power amplifier 804 is used for high speed serial readout of a linear sensor array 700. In addition, a cascode amplifier 808 is associated with each photodiode cell 800 of the image sensor array 700. The cascode amplifier 808 is of the type commonly referred to as a trans-impedance amplifier. This trans-impedance amplifier 808 is used to integrate charge, with high sensitivity and low noise. In the illustrated embodiment, the trans-impedance amplifier 808 comprises a first source transistor 40, a second transistor 816, a third transistor 818, a fourth transistor 820 and a reset capacitor (CR) 822. In the illustrated embodiment, the first source transistor 40 and second transistor 816 are CMOS P-device transistors having a gate width to length ratio of 2.6/1. The third transistor 818 and fourth transistor 820 are CMOS N-device transistors each having a gate width to length ratio of 1.4/1.
The drain of the first source transistor 40 is coupled to VDD 30. The gate of the first source transistor 40 is coupled to the third bias voltage VB3. The source of the first source transistor 40 is coupled to the drain of the second transistor 816. The gate of the second transistor 816 is coupled to the second bias voltage VB2. The source of the second transistor 816 is coupled to an output node 824. The source of the third transistor 818 is also coupled to the output node 824. The gate of the third transistor 818 is coupled to the first bias voltage VB1. The drain of the third transistor 818 is coupled to the source of the fourth transistor 820. The drain of the fourth transistor 820 is coupled to the anode terminal of the biasing diode 810 which has its cathode terminal coupled to ground 32.
The biasing diode 810 acts to bias the cascode amplifier 808 so that the voltage on the output node 824 is raised. This adjusts the output present at the output node 824 of the cascode amplifier 808 to a reasonable level.
The gate of the fourth transistor 820, which acts as the input to the cascode amplifier 808 is coupled to the cathode of the photodiode 704 through an input node 826. The reset capacitor (CR) 822 has its electrodes coupled across output node 824 and the input node 826.
The reset transistor 806 is a CMOS N-device transistor having a gate width to length ration of 0.8/0.6. The reset transistor 806 has its gate coupled to the reset signal ΦRX generated by the clock circuit 814. The drain of the reset transistor 806 is coupled to the input node 826 and the source of the reset transistor 806 is coupled to the output node 824. The reset transistor 806 acts to reset the cascode amplifier 808 by discharging the reset capacitor (CR) 822. The cascode amplifier 808 has a parasitic capacitance 828 represented in phantom lines in FIG. 8.
The details of operation of this circuit are discussed in other papers and textbooks and are not important for the understanding of the current source generating circuit 10 disclosed herein. However, those skilled in the art will recognize that the cascode amplifier 808 amplifies the output of the photodiode 704 and transfers a voltage, which is proportional to the integrated photo-generated charge, to the hold capacitor (CH) 44. The pass transistor 812 having its drain coupled to the output node 824 and source coupled to the hold node 830 controls the transfer of this voltage to the hold capacitor (CH) 44 in response to the state of the signal present on the gate of the transistor 812. The hold capacitor (CH) 44 is coupled between the hold node 830 and ground 32. The hold node 830 is also coupled to the input of the amplifier 804.
Those skilled in the art will recognize that the power of the cascode amplifiers 808 should preferably be minimized because of the large number of them on a chip. Despite the low power requirement, the cascode amplifier 808 must still be able to transfer the charge to the storage node 830, or hold capacitor (CH) 44, in a relatively short amount of time so as not to increase the readout line period anymore than necessary. If the sensor is designed for multiple speed operations, such as 1 MHz and 40 MHz, it is not desirable to penalize the lower power application with the power necessary for 40 MHz.
As an aid to further understanding the background to which the disclosed current generator relates, reference is made to the following U.S. patents, the disclosure of which are incorporated herein by this reference: U.S. Pat. No. 5,105,277 issued Apr. 14, 1992 to Hayes, et al. for a Sensor Array with Improved Uniformity; U.S. Pat. No. 5,081,536 issued Jan. 14, 1992 to Tandon, et al. for a Sensor Array with Improved Bias Charge Injection; and U.S. Pat. No. 4,737,854 issued Apr. 12, 1988 to Tandon, et al. for an Image Sensor Array with Two-Stage Transfer. U.S. Pat. Nos. 5,105,277, 5,081,536 and 4,737,854 explain the front end portion of the pixel circuits of other existing image sensor chips that are different than the front end of the pixel circuits 800 of FIG. 8.
The disclosed current source generator circuit generates a current source utilized used to set the power of an analog circuit. The current generated is adjusted to an appropriate level for varying operating conditions. A portion of the targeted analog circuit is used in the current source generator circuit. In addition, the current source generator circuit detects when the desired function of this analog circuit is completed. The current source generator circuit includes a master clock and a feedback loop to make the completion of the desired function happen slower or faster until the desired speed is obtained.
According to one aspect of the disclosure, a current source generator utilizing a portion of an analog circuit for driving the analog circuit to cyclically complete an analog function is disclosed. The current source generator comprises a portion of the analog circuit, a control clock circuit, a detection circuit, a phase weighted integrating circuit and a current source. The control clock circuit is used to start and stop the operation of the portion of the analog circuit. The detection circuit is configured to determine when the analog function is completed and provide an output indicative of the completion of the analog function. The phase weighted integrating circuit is driven by the output of the detection circuit and is configured to set an analog level that is function of the analog function completion time. The current source utilizes the analog level set by the integrating circuit as a reference level for driving the analog circuit to induce the analog circuit to complete the analog function at a desired speed.
According to another aspect of the disclosure, a current source generator utilizing a portion of a replicated analog circuit for driving the replicated analog circuit to cyclically complete an analog function is disclosed. The current source generator comprises a master clock, a portion of the replicated analog circuit, a current source and a feedback loop. The master clock has master clock speed of operation. The portion of the replicated analog circuit generates an output signal. The current source is configured to drive the portion of the replicated analog circuit. The feedback loop receives the output signal and generates an analog reference level output to the current source to induce the analog circuit function to be completed at a speed directly proportional to the master clock speed of operation.
According to yet another aspect of the disclosure, a reference level generator utilizing a portion of a replicated analog circuit for driving the replicated analog circuit to cyclically complete an analog function is disclosed. The reference level generator comprises a portion of the replicated analog circuit, a master clock, a control circuit, a detection circuit, an integrating circuit and a reference level circuit. The master clock operates at a master clock speed and provides master clock signals to the replicated analog circuit utilized to complete the analog function. The control circuit is used to start and stop the operation of the portion of the replicated analog circuit. The detection circuit is configured to determine when the analog function is completed and to provide an output indicative of the completion of the analog function. The integrating circuit is driven by the output of the detection circuit and configured to set an analog level that is function of the analog function completion time. The reference level circuit utilizes the analog level set by the integrating circuit for driving the replicated analog circuit to induce the replicated analog circuit to complete the analog function at a desired speed.
Additional features and advantages of the presently disclosed current source generator circuit will become apparent to those skilled in the art upon consideration of the following detailed description of embodiments exemplifying the best mode of carrying out the disclosure as presently perceived.
Corresponding reference characters indicate corresponding parts throughout the several views. Like reference characters tend to indicate like parts throughout the several views.